The present invention relates to a high density dynamic random access memory ("DRAM") and more specifically to a trench DRAM cell including a vertical transistor, thereby improving reliability and the electrical characteristics of the cell.
In order to form a high density DRAM, technology must be developed for maintaining in a small cell area the same storage capacitance as would be found in a low density DRAM. This could not be achieved by the conventional planar cell for memories with a capacity of 4 MB or more.
Therefore, to achieve a greater capacitance in a smaller cell area, trench capacitor and stacked capacitor technologies have been explored recently. However, most of the cell structures which have been studied so far have not satisfied the density requirements for DRAMs with a memory capacity of 64 MB or more because a transfer transistor is horizontally placed on the substrate and a storage capacitor is placed on the side of the transfer transistor.
To solve the above problem, the Composed Trench Transistor ("CTT") has been designed. As shown in FIG. 1a, the transfer transistor is vertically placed and the storage capacitor is placed under the transfer transistor in the CTT cell. However, in the fabrication step of the CTT cell, an isolation region between adjacent cells cannot be reduced because isolation between bit lines is performed by the Local Oxidation of Silicon ("LOCOS") method.
Further, FIG. 1b shows a cross-sectional view of a cell with a Surrounding Gate Transistor ("SGT") structure, which has been recently developed. In this cell structure, a transfer transistor with a vertical structure is placed on top of a silicon pillar and a high capacitance ("Hi-C") storage capacitor is placed under the silicon pillar. Therefore, isolation between adjacent cells is formed by trench isolation and a transfer transistor and a storage capacitor are all formed in the silicon pillar.
Although this SGT cell satisfied the requirements for a cell to accommodate a 64 MB DRAM, it was not immune to alpha particle-induced soft errors due to the Hi-C structure. Moreover, because the outside of the silicon pillar was highly doped with impurities associated with the high capacitance, the SGT cell had a problem in that the transfer transistor was electrically floating on the substrate due to the depletion region that occurs in the case of a small silicon pillar size (greater than 0.5 .mu.m)